`timescale	1ps/1ps
module s8_main_ctrl_01(
		input	wire		resetb,
		input	wire		sclk,

		input	wire		init_end,
		input	wire		input_active,
		input	wire		key_active,

		input	wire		fpga_rec_flag,
		input	wire		op_start_flag,
		input	wire	[31:0]	op_start_addr,
		
		//模式控制
		output	reg		init_mode,
		output	reg		test_mode,
		output	reg		reboot_en,
		output	reg		comm_en,

		output	wire	[7:0]	tout
		);

//************************************************/
//		参数定义
//************************************************/
//*************state******************************
parameter  IDLE_STATE		= 5'h01;
parameter  INIT_STATE		= 5'h02;
parameter  WAIT_STATE		= 5'h04;
parameter  NOMAL_STATE		= 5'h08;
parameter  TEST_STATE		= 5'h10;

parameter  REBOOT_ADDR		= 32'h10_00_00_00;

//**********************************************/
//		信号定义
/************************************************/
reg	[4:0]	main_state;
reg             init_start;
reg     [2:0]   init_st_count;
//************************************************/
//		状态控制
//************************************************/
//**************状态机*******************
always@(posedge sclk or negedge resetb)
	if(resetb == 0)
		main_state <= IDLE_STATE;
	else 
		case (main_state)
			IDLE_STATE:
			        if(init_start==1'b1)
				        main_state<=INIT_STATE;
			INIT_STATE:
				if (init_end==1)
					main_state<=WAIT_STATE;
			WAIT_STATE:
				if (input_active==1)
					main_state<=NOMAL_STATE;
				else if (key_active==1)
					main_state<=TEST_STATE;
			NOMAL_STATE:
				main_state<=NOMAL_STATE;
			TEST_STATE:
				if (input_active==1)
					main_state<=NOMAL_STATE;
			default: 
				main_state<=IDLE_STATE;
		endcase				
			
//************************************************/
//		信号选通
//************************************************/
always@(posedge sclk or negedge resetb)
	if(resetb == 0)
	        init_st_count<=0;
	else if(main_state==IDLE_STATE && init_st_count[2]==0)
                init_st_count<=init_st_count+1;

always@(posedge sclk)
        if(main_state!=IDLE_STATE)
                init_start<=1'b0;
        else if(init_st_count==3'h3)
                init_start<=1'b1;
                
always@(posedge sclk or negedge resetb)
	if(resetb == 0)
		init_mode<=0;
	else if (main_state==INIT_STATE)
		init_mode<=1;
	else
		init_mode<=0;
		
always@(posedge sclk or negedge resetb)
	if(resetb == 0)
		test_mode<=0;
	else if (main_state==TEST_STATE)
		test_mode<=1;
	else
		test_mode<=0;
		
always@(posedge sclk or negedge resetb)
	if(resetb == 0)
		reboot_en<=0;
	else if (op_start_flag==1 && fpga_rec_flag==1 && op_start_addr[28]==1)
		reboot_en<=1;
		
always@(posedge sclk or negedge resetb)
	if(resetb == 0)
		comm_en<=0;
	else if (main_state==WAIT_STATE || main_state==NOMAL_STATE)
		comm_en<=1;
	else
		comm_en<=0;
		
/************************************************/
//		测试信号
/************************************************/
assign	tout={init_end,main_state};

endmodule		